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max1294/MAX1296 ltqtz 7z ???z ???"%$  7????t|??????? ? ________________________________________________________________ maxim integrated products 1 19-1533; rev 1; 2/00 part max1294 acei max1294bcei 0? to +70? 0? to +70? temp. range pin-package 28 qsop 28 qsop  j ___________________________________ e?  ? _______________________________ inl (lsb) ?.5 ? a j ?^s?x???3??w7?tgl^?om?b{ 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 d10 d11 v dd ref refadj gnd com ch0 ch1 cs clk wr rd int d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 qsop top view MAX1296 pin configurations continued at end of data sheet. max1294aeei -40? to +85? 28 qsop ?.5 max1294beei -40? to +85? 28 qsop ? evaluation kit available MAX1296 aceg MAX1296bceg MAX1296aeeg -40? to +85? 0? to +70? 0? to +70? 24 qsop 24 qsop 24 qsop ?.5 MAX1296beeg -40? to +85? 24 qsop ? ?.5 ? ???a?? ? w1 ???????
max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? absolute maximum ratings electrical characteristics 7 %%  7  $0.(/% 3&'"%+7 %% 7 3&'  7  'dbqbdjupsbu3&'qjo g $-, .)[ evuzdzdmf
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stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v ch0?h5, com to gnd ............................-0.3v to (v dd + 0.3v) ref, refadj to gnd.................................-0.3v to (v dd + 0.3v) digital inputs to gnd ...............................................-0.3v to +6v digital outputs (d0?11, i nt ) to gnd.......-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70?) 24-pin qsop (derate 9.5mw/? above +70?)..........762mw 28-pin qsop (derate 8.00mw/? above +70?)........667mw operating temperature ranges max1294_c_ _/MAX1296_c_ _ .........................0? to +70? max1294_e_ _/MAX1296_e_ _ ......................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? external acquisition or external clock mode internal acquisition/internal clock mode max129_a external acquisition/internal clock mode external clock mode -3db rolloff sinad > 68db f in = 175khz (note 4) f in1 = 49khz, f in2 = 52khz max129_b no missing codes over temperature conditions ns 25 aperture delay ns 400 t acq t/h acquisition time 3.2 3.6 4 2.5 3.0 3.5 ? 2.1 t conv conversion time (note 5) mhz 6 full-power bandwidth khz 350 full-linear bandwidth db -78 channel-to-channel crosstalk db 76 imd intermodulation distortion db -80 sfdr spurious-free dynamic range total harmonic distortion (including 5th-order harmonic) db -80 thd ?.5 inl relative accuracy (note 2) bits 12 res resolution db 67 70 sinad signal-to-noise plus distortion lsb ?.2 channel-to-channel offset matching ppm/? ?.0 gain temperature coefficient lsb ? lsb ? dnl differential nonlinearity lsb ? offset error lsb ? gain error (note 3) units min typ max symbol parameter internal acquisition/internal clock mode external acquisition or external clock mode <200 ps <50 aperture jitter mhz 0.1 7.6 f clk external clock frequency % 30 70 duty cycle dc accuracy (note 1) dynamic specifications (f in(sine wave) = 50khz, v in = 2.5vp-p, 420ksps, external f clk = 7.6mhz, bipolar input mode) conversion rate 2 _______________________________________________________________________________________
i dd max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? electrical characteristics (continued) 7 %%  7  $0.(/% 3&'"%+7 %% 7 3&'  7  'dbqbdjupsbu3&'qjo g $-, .)[ evuzdzdmf
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conditions units min typ max symbol parameter shutdown mode v ref = 2.5v, f sample = 420ksps 0 to 0.5ma output load to power down the internal reference for small adjustments on/off-leakage current, v in = 0 or v dd unipolar, v com = 0 bipolar, v com = v ref /2 2 ? 200 300 i ref v 1.0 v dd + 50mv v ref ref input voltage range ? 4.7 10 capacitive bypass at ref ? 0.01 1 capacitive bypass at refadj mv/ma 0.2 0.5 load regulation (note 7) v v dd - 1 refadj high threshold mv ?00 refadj input range ppm/? ?0 tc ref ref temperature coefficient ma 15 ref short-circuit current v 2.49 2.5 2.51 ref output voltage pf 12 c in input capacitance ? ?.01 ? multiplexer leakage current v 0 v ref v in analog input voltage range single-ended and differential (note 6) -v ref /2 +v ref /2 cs = v dd i source = 1ma i sink = 1.6ma v in = 0 or v dd ? ?.1 ? i leakage three-state leakage current v v dd - 0.5 v oh output voltage high v 0.4 v ol output voltage low pf 15 c in input capacitance ? ?.1 ? i in input leakage current mv 200 v hys input hysteresis v 0.8 v il input voltage low v 4.0 v ih input voltage high cs = v dd v 4.5 5.5 v dd analog supply voltage pf 15 c out three-state output capacitance 2.6 2.9 ref input current ? external reference 2.2 2.5 external reference 0.5 0.8 ma internal reference 1.0 1.2 power-supply rejection psr v dd = 5v ?0%, full-scale input ?.3 ?.7 mv positive supply current i dd shutdown mode 210 ? analog inputs internal reference external reference at ref digital inputs and outputs power requirements internal reference operating mode, f sample = 420ksps standby mode _______________________________________________________________________________________ 3
max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? 4 _______________________________________________________________________________________ t tr 10 40 ns c load = 20pf, figure 1 rd rise to output disable wr to clk fall setup time t cws 60 ns ns clk pulse width high ns clk period t ch 40 rd fall to output data valid t do 10 50 ns rd fall to int high delay t int1 50 ns cs fall to output data valid t do2 100 ns c load = 20pf, figure 1 c load = 20pf, figure 1 c load = 20pf, figure 1 t cp 132 clk pulse width low t cl 40 ns data valid to wr rise time t ds 40 ns wr rise to data valid hold time t dh 0 ns clk fall to wr hold time t cwh 40 ns cs to clk or wr setup time t csws 40 ns clk or wr to cs hold time t cswh 0 ns cs pulse width t cs 100 ns wr pulse width (note 8) t wr 60 ns t tc 10 60 ns c load = 20pf, figure 1 parameter symbol min typ max units conditions cs rise to output disable note 1: tested at v dd = +5v, com = gnd, unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. note 3: offset nulled. note 4: on channel is grounded; sine wave applied to off channels. note 5: conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. note 6: input voltage range referenced to negative input. the absolute range for the analog inputs is from gnd to v dd . note 7: external load should not change during conversion for specified accuracy. note 8: when bit 5 is set low for internal acquisition, wr must not return low until after the first falling clock edge of the conversion. timing characteristics 7 %%  7  $0.(/% 3&'"%+7 %% 7 3&'  7  'dbqbdjupsbu3&'qjo g $-, .)[ evuzdzdmf
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3k 3k dout dout v dd a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol c load 20pf c load 20pf
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max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? _______________________________________________________________________________________ 5 -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 1000 3000 4000 5000 integral nonlinearity vs. digital output code max1294/6-01 digital output code inl (lsb) -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 1000 3000 4000 5000 differential nonlinearity vs. digital output code max1294/6-02 digital output code dnl (lsb) 1.8 1.9 2.0 2.1 2.2 supply current vs. supply voltage max1294/6 toc03 v dd (v) i dd (ma) 4.50 5.00 4.75 5.25 5.50 r l = code = 101010100000 1.7 1.9 1.8 2.1 2.0 2.2 2.3 -40 10 -15 35 60 85 supply current vs. temperature max1294/6 toc04 temperature (?) i dd (ma) r l = code = 101010100000 930 950 940 970 960 980 990 4.50 5.00 4.75 5.25 5.50 standby current vs. supply voltage max1294/6 toc05 v dd (v) standby i dd ( a) 930 950 940 970 960 980 990 -40 10 -15 356085 standby current vs. temperature max1294/6 toc06 temperature ( c) standby i dd ( a) 1.0 1.5 2.0 2.5 3.0 power-down current vs. supply voltage max1290/2 toc07 v dd (v) power-down i dd ( a) 4.50 5.00 4.75 5.25 5.50 1.8 2.0 1.9 2.1 2.2 -40 10 -15 356085 power-down current vs. temperature max1294/6 toc08 temperature ( c) power-down i dd ( a) a j ?^ ?
q ______________________________________________________________________ (v dd = +5v, v ref = +2.500v, f clk = 7.6mhz, c l = 20pf, t a = +25?, unless otherwise noted.) 0.1 1k 100k 10 1 100 10k 1m supply current vs. sample frequency max1294/6-02a f sample (hz) i dd ( a) 0 10 100 1000 10,000 with external reference with internal reference
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_________________________________________________________________ (v dd = +5v, v ref = +2.500v, f clk = 7.6mhz, c l = 20pf, t a = +25?, unless otherwise noted.) 2.48 2.49 2.50 2.52 2.51 2.53 reference voltage vs. temperature max1294/6-10 temperature ( c) v ref (v) -40 35 -15 10 60 85 -1.0 0 -0.5 0.5 1.0 offset error vs. supply voltage max1294/6 toc11 v dd (v) offset error (lsb) 4.50 5.00 4.75 5.25 5.50 -2 -1 0 1 2 offset error vs. temperature max1294/6 toc12 temperature ( c) offset error (lsb) -40 35 60 -15 10 85 -2 0 -1 1 2 gain error vs. supply voltage max1294/6 toc13 v dd (v) gain error (lsb) 4.50 5.00 4.75 5.25 5.50 0 0.5 1.0 1.5 2.0 gain error vs. temperature max1294/6 toc14 temperature ( c) gain error (lsb) -40 35 60 -15 10 85 2.48 2.49 2.51 2.50 2.52 2.53 internal reference voltage vs. supply voltage max1294/6-09 v dd (v) v ref (v) 4.50 5.00 4.75 5.25 5.50 -140 -120 -100 -80 -60 -40 -20 0 20 0 200 400 600 800 1000 fft plot max1294/6-15 frequency (khz) amplitude (db) v dd = 5v f in = 50khz f sample = 400ksps
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max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? _______________________________________________________________________________________ 9 bit pd1, pd0 0 d7, d6 pd1 and pd0 select the various clock and power-down modes. full power-down mode. clock mode is unaffected. d5 acqmod acqmod = 0: internal acquisition mode acqmod = 1: external acquisition mode name functional description 0 1 0 standby power-down mode. clock mode is unaffected. 0 1 1 normal operation mode. external clock mode selected. 1 normal operation mode. internal clock mode selected. d4 sgl /dif sgl /dif = 0: pseudo-differential analog input mode sgl /dif = 1: single-ended analog input mode in single-ended mode, input signals are referred to com. in pseudo-differential mode, the voltage difference between two channels is measured (see tables 2, 4). d3 uni /bip uni/ bip = 0: bipolar mode uni/ bip = 1: unipolar mode in unipolar mode, an analog input signal from 0v to v ref can be converted; in bipolar mode, the signal can range from -v ref /2 to +v ref /2. d2, d1, d0 a2, a1, a0 address bits a2, a1, a0 select which of the 6/2 (max1294/MAX1296) channels is to be converted (see tables 2, 3). 
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max1294/MAX1296 12 ______________________________________________________________________________________ t cs t csws t wr t acq t conv t dh t ds t nt1 t d0 t tr t csloh acqmod = "1" cs wr d11 d0 int rd dout high-z high-z acqmod = "0" valid data control byte control byte
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max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? ______________________________________________________________________________________ 13 ? ????t?? ? ????t???
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wr clk clk wr wr goes high when clk is high wr goes high when clk is low t cws t ch t cl t cp t cwh acquisition starts acquisition starts conversion starts conversion starts acquisition ends acquisition ends acqmod = "0" acqmod = "0" wr clk clk wr wr goes high when clk is high wr goes high when clk is low t dh t dh t cwh t cws acquisition starts acquisition starts conversion starts conversion starts acquisition ends acquisition ends acqmod = "1" acqmod = "1" acqmod = "0" acqmod = "0"
max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? 14 ______________________________________________________________________________________ ??????
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m??????? v dd = +5v 330k 50k 50k 0.01f 4.7f refadj ref max1294 MAX1296
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?  +5v +5v gnd supplies dgnd +5v com gnd 4.7 f 0.1 f v dd digital circuitry max1294 MAX1296 r* = 5 ? *optional clk acquisition control word conversion d11 d0 acquisition sampling instant 123 4 5 6 78 910111213141516 wr rd d7 d0 state control word d11 d0 ltqtz 7z ???z???"%$  7????t|??????? ?
max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? ______________________________________________________________________________________ 17 ;?w [ _____________________________
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r w 3.4 ?w zpb{ thd v v v v v =+++ ? ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log / ?? ?c _____________________________ transistor count: 5781 substrate connected to gnd
max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? 18 ______________________________________________________________________________________ a j ?^s? ______________________________________________________________________ v dd ref refadj int ch5 ch4 ch3 ch2 ch1 ch0 com gnd 4.7 f 0.1 f +5v +2.5v output status p control inputs clk cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 p data bus d8 d9 d10 d11 analog inputs max1294 v dd ref refadj int ch1 ch0 com gnd 4.7 f 0.1 f +5v +2.5v output status p control inputs clk cs wr rd d7 d6 d5 d4 d3 d2 d1 d0 p data bus d8 d9 d10 d11 analog inputs MAX1296 e?  ? v
__________________________ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d10 d11 v dd ref refadj gnd cs com ch0 ch1 ch2 ch3 ch4 ch5 clk wr rd int d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 qsop top view max1294
max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? ______________________________________________________________________________________ 19 ?-? ________________________________________________________________________ qsop.eps
max1294/MAX1296 ltqtz 7z ???z???"%$  7????t|??????? ? ?3tpx
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5's`ts?t|?7?!?b?vb?-y`?b{ 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2000 maxim integrated products is a registered trademark of maxim integrated products. notes b  eg 3 ?   f? n y s
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